`timescale 1ns / 1ps /* * File : RegisterFilenHSE.v * Project : Stefan cel Mare University of Suceava, WH_nMPRA_RTOS core Project * Creator(s) : Zagan Ionel * Modification History: * Rev Date Initials Description of Change * 1.0 7-Jun-2021 ZI Initial design. * 2.0 11-Mar-2022 ZI nMPRA registers revision * Standards/Formatting: * Verilog 2001, 4 soft tab, wide column. * */ module RegisterFilenHSE #(parameter NR_TASKS = 4)( input clock, input reset, input [7:0] ID_nHSE_Task_Select, input [3:0] ExtIntEv, input [5:0] OpCode, input [4:0] Rs, input [4:0] Rt, input [15:0] Immediate, input [31:0] Instruction_WB, input [4:0] Write_Reg_RtRd_WB, input [31:0] Write_Data_WB, input [31:0] Write_Data_WB_GPR, input Reg_Write_nHSE_WB, // input [31:0] ID_ReadData2_RF, // output reg [31:0] Read_Data_from_nHSE, output [31:0] grSSF, // output reg [7:0] nHSE_sCPUi_Select, output reg nHSE_EN_sCPUi, output nHSE_Fetch_I, output reg [31:0] PC_nHSE_Out, output reg PC_nHSE_Sel ); `include "nHSE_MIPS_Parameters.v" //IDs instPi localparam [7:0] sCPU0_ID=0, sCPU1_ID=1, sCPU2_ID=2, sCPU3_ID=3, sCPU4_ID=4, sCPU5_ID=5, sCPU6_ID=6, sCPU7_ID=7, sCPU8_ID=8, sCPU9_ID=9, sCPU10_ID=10, sCPU11_ID=11, sCPU12_ID=12, sCPU13_ID=13, sCPU14_ID=14, sCPU15_ID=15; //Current_nHSE_FSMstate states localparam [7:0] FSM_WAIT=255, FSM_sCPU0=0, FSM_sCPU1=1, FSM_sCPU2=2, FSM_sCPU3=3; //nHSE registers //local nHSE registers reg [31:0] crTRi [0:NR_TASKS-1]; //Task Register reg [31:0] crEVi [0:NR_TASKS-1]; //Events Register reg [31:0] crEPRi[0:NR_TASKS-1]; //Enable Priority Register reg [31:0] cr0D1; //Deadline 1 reg [31:0] cr0D2; //Deadline 2 reg [31:0] cr0MSTOP; //Master stop reg [31:0] cr0RESET; reg [31:0] cr0CPUID; //------------------------------------------- reg [31:0] grMutexi [0:NR_MUTEX-1]; reg [31:0] crEMRi0 [0:NR_TASKS-1]; //reg [31:0] crEMRi1[0:NR_TASKS-1]; //reg [31:0] crEMRi2[0:NR_TASKS-1]; //reg [31:0] crEMRi3[0:NR_TASKS-1]; //-------------------------------------------- reg [31:0] grSSRi [0:NR_EV-1]; reg [31:0] grSSF; //event full register reg [31:0] crESSRi0 [0:NR_TASKS-1]; //reg [31:0] crESSRi1[0:NR_TASKS-1]; //reg [31:0] crESSRi2[0:NR_TASKS-1]; //reg [31:0] crESSRi3[0:NR_TASKS-1]; reg [31:0] crSSRindex [0:NR_TASKS-1]; //-------------------------------------------- //local registers reg [31:0] mrPRIsCPUi [0:NR_TASKS-1]; reg [31:0] mrTEVi [0:NR_TASKS-1]; reg [31:0] mrWDEVi [0:NR_TASKS-1]; reg [31:0] mrD1EVi [0:NR_TASKS-1]; reg [31:0] mrD2EVi [0:NR_TASKS-1]; //-------------------------------------------- reg [63:0] mrCntRuni [0:NR_TASKS-1]; //Run cycle value register reg [63:0] mrCntSleepi[0:NR_TASKS-1]; reg [63:0] mr0CntSleep; //-------------------------------------------- reg [31:0] mrCommRegij[0:NR_REG_INTERTASK_COMM*NR_TASKS-1]; //------------------------------------------//Intertask communication register //Global registers reg [31:0] grINT_IDi [0:NR_INT-1]; reg [31:0] grINTi_EV; //---------------------------------------------- reg [7:0] index_FreeSignal; reg [2:0] grEv_select_sCPU[0:NR_TASKS-1]; reg [7:0] grInt_select_sCPU[0:NR_TASKS-1]; reg [31:0] Timer0 [0:NR_TASKS-1]; reg [31:0] Timer1 [0:NR_TASKS-1]; reg [31:0] grINT_PR; //-------------------------------------------- reg [31:0] sCPUi_Lower_PRI; reg [31:0] nHSE_sCPUi_Ready; reg [7:0] nHSE_FSM_state; reg Inhibit_Context_Switch; integer i, i_sCPU_m, i_mutex, i_dinamic0, i_dinamic1; integer i_INT0, i_INT1, i_INT2, i_INT3, i_INT_0, i_INT_1, i_INT_2; integer j, j_w, i_INT_, i_S0, i_S1, i_S2, i_S3, i_S, init_INT, init_M, init_E; integer i_WAIT,i_sCPU, i_sCPU0, i_sCPU1, i_sCPU2, i_sCPU3; //---------------------------------------------- wire [31:0] EXC_Vector_Base_INTi [0:NR_INT-1]; // wire [5:0] WB_OpCode = Instruction_WB[31:26]; wire [4:0] WB_Rs = Instruction_WB[25:21]; wire [4:0] WB_Rt = Instruction_WB[20:16]; wire [4:0] WB_Rd = Instruction_WB[15:11]; wire [15:0] WB_Immediate = Instruction_WB[15:0]; wire Scheduler_Static_Dynamic; wire [31:0] Wire_Mask1_bit_i [0:31]; wire [31:0] Wire_Mask0_bit_i [0:31]; wire [3:0] sCPUi_ID [0:NR_TASKS-1]; wire [5:0] FSM_sCPUi [0:NR_TASKS-1]; // wire [31:0] crEPRi0; wire [31:0] crEPRi1; wire [31:0] crEPRi2; wire [31:0] crEPRi3; // assign Scheduler_Static_Dynamic = ((mrPRIsCPUi[0] | mrPRIsCPUi[1] | mrPRIsCPUi[2] | mrPRIsCPUi[3])== 32'h00000000) ? 1'b0 : 1'b1; //nHSE_sCPUi_Select assign nHSE_Fetch_I = (nHSE_FSM_state == ID_nHSE_Task_Select) ? 1'b1 : 1'b0; // assign crEPRi0 = crEPRi[0]; assign crEPRi1 = crEPRi[1]; assign crEPRi2 = crEPRi[2]; assign crEPRi3 = crEPRi[3]; // assign sCPUi_ID[0] = sCPU0_ID; assign sCPUi_ID[1] = sCPU1_ID; assign sCPUi_ID[2] = sCPU2_ID; assign sCPUi_ID[3] = sCPU3_ID; //... // assign FSM_sCPUi[0] = FSM_sCPU0; assign FSM_sCPUi[1] = FSM_sCPU1; assign FSM_sCPUi[2] = FSM_sCPU2; assign FSM_sCPUi[3] = FSM_sCPU3; // assign EXC_Vector_Base_INTi[0] = EXC_Vector_Base_INT0; assign EXC_Vector_Base_INTi[1] = EXC_Vector_Base_INT1; assign EXC_Vector_Base_INTi[2] = EXC_Vector_Base_INT2; assign EXC_Vector_Base_INTi[3] = EXC_Vector_Base_INT3; //--------------------------------------- initial begin for(i=0;i>32)&64'h00000000FFFFFFFF : (mrCntRuni[ID_nHSE_Task_Select]>>32)&64'h00000000FFFFFFFF;//H end 5'b01000: begin Read_Data_from_nHSE <= (ID_nHSE_Task_Select == 0)? mrCntSleepi[Immediate]&64'h00000000FFFFFFFF : mrCntSleepi[ID_nHSE_Task_Select]&64'h00000000FFFFFFFF;//L }[31:0] end 5'b01001: begin Read_Data_from_nHSE <= (ID_nHSE_Task_Select == 0)? (mrCntSleepi[Immediate]>>32)&64'h00000000FFFFFFFF : (mrCntSleepi[ID_nHSE_Task_Select]>>32)&64'h00000000FFFFFFFF;//H }[31:0] end 5'b01010: begin Read_Data_from_nHSE <= mr0CntSleep[31:0];//L end 5'b01011: begin Read_Data_from_nHSE <= mr0CntSleep[63:32];//H end 5'b01100: begin Read_Data_from_nHSE <= (ID_nHSE_Task_Select == 0)? mrCommRegij[Immediate]:mrCommRegij[ID_nHSE_Task_Select]; end 5'b01101: begin Read_Data_from_nHSE <= (ID_nHSE_Task_Select == 0)? {29'b00000000000000000000000000000, grEv_select_sCPU[Immediate]}:{29'b00000000000000000000000000000, grEv_select_sCPU[ID_nHSE_Task_Select]}; end 5'b01110: begin Read_Data_from_nHSE <= (ID_nHSE_Task_Select == 0)? {24'b000000000000000000000000, grInt_select_sCPU[Immediate]}:{24'b000000000000000000000000, grInt_select_sCPU[ID_nHSE_Task_Select]}; end default :begin Read_Data_from_nHSE <= 32'h00000000; end endcase end Rs_Type_CFC2 : begin //Copy from COP2, GPR[rt] <- CP2CCR[Impl] case (Immediate) 16'h0000: begin //TRi(nHSE_index)->GPR[Rt] Read_Data_from_nHSE <= crTRi[ID_nHSE_Task_Select]; end 16'h0001: begin //TRi(nHSE_index)->GPR[Rt] Read_Data_from_nHSE <= crEVi[ID_nHSE_Task_Select]; end 16'h0002: begin // Rj <- EPR(i) Read_Data_from_nHSE <= crEPRi[ID_nHSE_Task_Select]; end 16'h0003: begin //Rj <- cr0D1 if(ID_nHSE_Task_Select == 0) Read_Data_from_nHSE <= cr0D1; end 16'h0004: begin //Rj <- cr0D2 if(ID_nHSE_Task_Select == 0) Read_Data_from_nHSE <= cr0D2; end 16'h0005: begin //Rj<-MSTOP if(ID_nHSE_Task_Select == 0) Read_Data_from_nHSE <= cr0MSTOP; end 16'h0006: begin //Rj <- RESET if(ID_nHSE_Task_Select == 0) Read_Data_from_nHSE <= cr0RESET; end 16'h0007: begin //Rj <- CPUID if(ID_nHSE_Task_Select == 0) Read_Data_from_nHSE <= cr0CPUID; end 16'h0008: begin //Rj<-EMR(i)0 Read_Data_from_nHSE <= crEMRi0[ID_nHSE_Task_Select]; end 16'h000C: begin //Rj<-EER(i)0 Read_Data_from_nHSE <= crESSRi0[ID_nHSE_Task_Select]; end default :begin Read_Data_from_nHSE <= 32'h00000000; end endcase end default : begin Read_Data_from_nHSE <= 32'h00000000; end endcase end default : begin Read_Data_from_nHSE <= 32'h00000000; end endcase //end case(OpCode) end always @(posedge clock) begin if (reset) begin for(i_sCPU=0;i_sCPUTRi(nHSE_index) crTRi[ID_nHSE_Task_Select] <= crTRi[ID_nHSE_Task_Select] & Write_Data_WB;//instr wait end 16'h0001: begin //GPR[Rt]->TRi(nHSE_index) crEVi[ID_nHSE_Task_Select] <= crEVi[ID_nHSE_Task_Select] & Write_Data_WB; end 16'h0002: begin // CTC2 Rj, EPRi ; efect EPR(i)<-Rj crEPRi[ID_nHSE_Task_Select] <= Write_Data_WB; end 16'h0003: begin // CTC2 Rj, cr0D1 ; efect cr0D1 <- Rj if(ID_nHSE_Task_Select == 0) begin cr0D1 <= Write_Data_WB; end end 16'h0004: begin //instr CTC2 Rj, cr0D2 ; efect cr0D2 <- Rj if(ID_nHSE_Task_Select == 0) begin cr0D2 <= Write_Data_WB; end end 16'h0005: begin //instr CTC2 Rj, MSTOP; efect MSTOP<-Rj if(ID_nHSE_Task_Select == 0) begin cr0MSTOP <= Write_Data_WB; end end 16'h0006: begin //instr CTC2 Rj, RESET; efect RESET<-Rj if(ID_nHSE_Task_Select == 0) begin cr0RESET <= Write_Data_WB; end end 16'h0008: begin //instr CTC2 Rj, EMRi0 ; efect EMR(i)0<- Rj crEMRi0[ID_nHSE_Task_Select] <= crEMRi0[ID_nHSE_Task_Select] & Write_Data_WB; end 16'h000C: begin //instr CTC2 Rj, EERi (nHSE); efect EER(i)<-Rj crESSRi0[ID_nHSE_Task_Select] <= Write_Data_WB; end default :begin end endcase end //end Rs_Type_CTC2 endcase //end case (WB_Rs) end //end Op_Type_CP2 Op_Type_LWC2:begin //Load Word to COP2 case (WB_Rt) 5'b00000:begin //INT Inhibit_Context_Switch <= 1'b0; grINT_IDi[WB_Immediate] <= (Reg_Write_nHSE_WB)? Write_Data_WB: grINT_IDi[WB_Immediate]; end 5'b00001:begin //mutex Inhibit_Context_Switch <= 1'b0; if(Write_Data_WB_GPR == 32'h00000001) begin grMutexi[WB_Immediate] <= (Reg_Write_nHSE_WB)? Write_Data_WB: grMutexi[WB_Immediate]; end end 5'b00010:begin //semnale Inhibit_Context_Switch <= 1'b0; if((Write_Data_WB&32'h80000000) == 32'h80000000)begin if((grSSF == 32'h00000000) &(((Write_Data_WB & 32'h7C000000)>>26) == {28'h0000000,ID_nHSE_Task_Select}) &(((Write_Data_WB & 32'h03E00000)>>21) < NR_TASKS) &((cr0MSTOP & Wire_Mask1_bit_i[((Write_Data_WB & 32'h03E00000)>>21)])!=32'h00000000) ) begin grSSRi[index_FreeSignal] <= (Reg_Write_nHSE_WB)? Write_Data_WB: grSSRi[index_FreeSignal]; end end else begin if(((grSSRi[WB_Immediate] & 32'h03E00000)>>21) == {28'h0000000,ID_nHSE_Task_Select})begin grSSRi[WB_Immediate] <= (Reg_Write_nHSE_WB)? Write_Data_WB: grSSRi[WB_Immediate]; end end end 5'b00011:begin //grSSF <= (Reg_Write_nHSE_WB)? Write_Data_WB: grSSF; Inhibit_Context_Switch <= 1'b0; end 5'b00100:begin //grINT_PR <= (Reg_Write_nHSE_WB)? Write_Data_WB: grINT_PR; Inhibit_Context_Switch <= 1'b0; end default :begin Inhibit_Context_Switch <= 1'b0; end endcase end Op_Type_SWC2:begin //Store Word from COP2 case (WB_Rt) 5'b00000:begin //INT Inhibit_Context_Switch <= 1'b0; end 5'b00001:begin //mutex Inhibit_Context_Switch <= 1'b0; end 5'b00010:begin //semnale Inhibit_Context_Switch <= 1'b0; if(crSSRindex[ID_nHSE_Task_Select] != 32'hFFFFFFFF) grSSRi[crSSRindex[ID_nHSE_Task_Select]] <= 32'h00000000; end 5'b00011: Inhibit_Context_Switch <= 1'b0; 5'b00100: Inhibit_Context_Switch <= 1'b0; //grINT_PR default :begin Inhibit_Context_Switch <= 1'b0; end endcase end endcase //end case(WB_OpCode) // end //--------------------------------------------------------------------------------------------- //write register "Read_Data_from_nHSE" //--------------------------------------------------------------------------------------------- case (OpCode) Op_Type_SWC2:begin //Store Word from COP2; case (Rt) 5'b00000: begin //INT //Inhibit_Context_Switch <= 1'b1; end 5'b00001: begin Inhibit_Context_Switch <= 1'b1; end 5'b00010: begin if(crSSRindex[ID_nHSE_Task_Select] != 32'hFFFFFFFF) Inhibit_Context_Switch <= 1'b1; //Immediate else Inhibit_Context_Switch <= 1'b0; end 5'b00011: begin //Inhibit_Context_Switch <= 1'b1; end 5'b00100: begin //Inhibit_Context_Switch <= 1'b1; end default : begin Inhibit_Context_Switch <= 1'b0; end endcase end Op_Type_LWC2:begin //Load Word to COP2; case (Rt) //Rs 5'b00000:begin //INT //Inhibit_Context_Switch <= 1'b1; end 5'b00001:begin //mutex if(((grMutexi[Immediate]&32'h80000000)== 32'h80000000) &((grMutexi[Immediate]&32'h7FFFFFFF)!= ID_nHSE_Task_Select)) begin crEMRi0[ID_nHSE_Task_Select] <= crEMRi0[ID_nHSE_Task_Select] | Wire_Mask1_bit_i[Immediate]; CTC2 crTRi[ID_nHSE_Task_Select] <= crTRi[ID_nHSE_Task_Select] | 32'h00000020; Inhibit_Context_Switch <= 1'b0; end else begin Inhibit_Context_Switch <= 1'b1; //---- end end 5'b00010:begin //grSSRi if(grSSF == 32'h00000000) begin Inhibit_Context_Switch <= 1'b1; end else begin Inhibit_Context_Switch <= 1'b0; end end 5'b00011:begin end 5'b00100:begin //grINT_PR end default : begin Inhibit_Context_Switch <= 1'b0; end endcase end default : begin end endcase //end case(OpCode) //--------------------------------------------------------------------------------------------- //time events //--------------------------------------------------------------------------------------------- for(j_w=0;j_w= mrWDEVi[j_w]) && ((crTRi[j_w] & Mask1_bit1)!= 32'h00000000)) begin crEVi[j_w] <= crEVi[j_w] | Mask1_bit1; Timer1[j_w] <= 32'h00000000; end end for(j=0;j= mrTEVi[j]) && ((crTRi[j] & Mask1_bit0)!= 32'h00000000)) begin crEVi[j] <= crEVi[j] | Mask1_bit0; Timer0[j] <= 32'h00000000; end //deadline 1 if((Timer0[j] == mrD1EVi[j]) && ((crTRi[j] & Mask1_bit2)!= 32'h00000000)) begin crEVi[j] <= crEVi[j] | Mask1_bit2; cr0D1[j] <= cr0D1[j] | Wire_Mask1_bit_i[j]; end //deadline 2 if((Timer0[j] == mrD2EVi[j]) && ((crTRi[j] & Mask1_bit3)!= 32'h00000000)) begin // Deadline 2 crEVi[j] <= crEVi[j] | Mask1_bit3; cr0D2[j] <= cr0D2[j] | Wire_Mask1_bit_i[j]; end if(ID_nHSE_Task_Select == j[3:0]) begin if(nHSE_EN_sCPUi)begin mrCntRuni[j] <= mrCntRuni[j] + 1; end else begin mrCntSleepi[j]<= mrCntSleepi[j] + 1; end end else begin mrCntSleepi[j]<= mrCntSleepi[j] + 1; end end //end for //--------------------------------------------------------------------------------------------- // //--------------------------------------------------------------------------------------------- if(nHSE_EN_sCPUi == DISABLE) begin mr0CntSleep <= mr0CntSleep + 1; end //--------------------------------------------------------------------------------------------- //int //--------------------------------------------------------------------------------------------- for(i_INT_=0;i_INT_=0;i_S1=i_S1-1) begin if((grSSRi[i_S1] & 32'h80000000) == 32'h00000000) index_FreeSignal <= i_S1; end for(i_S2=0;i_S2=0;i_S3=i_S3-1) begin if((grSSRi[i_S3] & 32'h80000000) == 32'h80000000) //if it's an active signal crSSRindex[((grSSRi[i_S3] & 32'h03E00000)>>21)] = i_S3; end for(i_S=0;i_S>21)] & Mask1_bit6)!= 32'h00000000))begin crEVi[((grSSRi[i_S] & 32'h03E00000)>>21)] <= crEVi[((grSSRi[i_S] & 32'h03E00000)>>21)] | Mask1_bit6; end end end //--------------------------------------------------------------------------------------------- // //--------------------------------------------------------------------------------------------- for(i_dinamic0=0;i_dinamic0=0;i_INT0=i_INT0-1) begin if((grINT_IDi[i_INT0] == sCPU0_ID)) begin if(grEv_select_sCPU[sCPU0_ID] == 3'b111) begin grEv_select_sCPU[sCPU0_ID] <= 3'b100; crEVi[sCPU0_ID] <= crEVi[sCPU0_ID] | 32'h00000080; crTRi[sCPU0_ID] <= crTRi[sCPU0_ID] | 32'h00000080; if(grInt_select_sCPU[sCPU0_ID] == 8'hFF)begin PC_nHSE_Out <= EXC_Vector_Base_INTi[i_INT0]; PC_nHSE_Sel <= 1'b1; grInt_select_sCPU[sCPU0_ID] <= i_INT0; Inhibit_Context_Switch <= 1'b0; end end else begin PC_nHSE_Sel <= 1'b0; if((Reg_Write_nHSE_WB==1)&(WB_OpCode==Op_Type_CP2)&(WB_Rs==Rs_Type_CTC2)&((WB_Immediate == 16'h0001)&((Write_Data_WB&32'h00000080)== 32'h00000000))) begin grInt_select_sCPU[sCPU0_ID] <= 8'hFF; grEv_select_sCPU[sCPU0_ID] <= 3'b111; end end end end //for end //if else if(((crTRi[sCPU0_ID] & Mask1_bit5)&&(crEVi[sCPU0_ID] & Mask1_bit5))&& (~((crEPRi0[20:18]=0;i_INT1=i_INT1-1) begin if((grINT_IDi[i_INT1] == sCPU1_ID)) begin if(grEv_select_sCPU[sCPU1_ID] == 3'b111) begin grEv_select_sCPU[sCPU1_ID] <= 3'b100; crEVi[sCPU1_ID] <= crEVi[sCPU1_ID] | 32'h00000080; crTRi[sCPU1_ID] <= crTRi[sCPU1_ID] | 32'h00000080; if(grInt_select_sCPU[sCPU1_ID] == 8'hFF)begin PC_nHSE_Out <= EXC_Vector_Base_INTi[i_INT1]; grInt_select_sCPU[sCPU1_ID] <= i_INT1; PC_nHSE_Sel <= 1'b1; Inhibit_Context_Switch <= 1'b0; end end else begin PC_nHSE_Sel <= 1'b0; if((Reg_Write_nHSE_WB==1)&(WB_OpCode==Op_Type_CP2)&(WB_Rs==Rs_Type_CTC2)&((WB_Immediate == 16'h0001)&((Write_Data_WB&32'h00000080)== 32'h00000000))) begin grInt_select_sCPU[sCPU1_ID] <= 8'hFF; grEv_select_sCPU[sCPU1_ID] <= 3'b111; end end end end //for end else if(((crTRi[sCPU1_ID] & Mask1_bit5)&&(crEVi[sCPU1_ID] & Mask1_bit5))&& (~((crEPRi1[20:18]=0;i_INT2=i_INT2-1) begin if((grINT_IDi[i_INT2] == sCPU2_ID)) begin if(grEv_select_sCPU[sCPU2_ID] == 3'b111) begin grEv_select_sCPU[sCPU2_ID] <= 3'b100; crEVi[sCPU2_ID] <= crEVi[sCPU2_ID] | 32'h00000080; crTRi[sCPU2_ID] <= crTRi[sCPU2_ID] | 32'h00000080; if(grInt_select_sCPU[sCPU2_ID] == 8'hFF)begin PC_nHSE_Out <= EXC_Vector_Base_INTi[i_INT2]; grInt_select_sCPU[sCPU2_ID] <= i_INT2; PC_nHSE_Sel <= 1'b1; Inhibit_Context_Switch <= 1'b0; end end else begin PC_nHSE_Sel <= 1'b0; if((Reg_Write_nHSE_WB==1)&(WB_OpCode==Op_Type_CP2)&(WB_Rs==Rs_Type_CTC2)&((WB_Immediate == 16'h0001)&((Write_Data_WB&32'h00000080)== 32'h00000000))) begin grInt_select_sCPU[sCPU2_ID] <= 8'hFF; grEv_select_sCPU[sCPU2_ID] <= 3'b111; end end end end //for end //if else if(((crTRi[sCPU2_ID] & Mask1_bit5)&&(crEVi[sCPU2_ID] & Mask1_bit5))&& (~((crEPRi2[20:18]=0;i_INT3=i_INT3-1) begin if((grINT_IDi[i_INT3] == sCPU3_ID)) begin if(grEv_select_sCPU[sCPU3_ID] == 3'b111) begin grEv_select_sCPU[sCPU3_ID] <= 3'b100; crEVi[sCPU3_ID] <= crEVi[sCPU3_ID] | 32'h00000080; crTRi[sCPU3_ID] <= crTRi[sCPU3_ID] | 32'h00000080; if(grInt_select_sCPU[sCPU3_ID] == 8'hFF)begin PC_nHSE_Out <= EXC_Vector_Base_INTi[i_INT3]; grInt_select_sCPU[sCPU3_ID] <= i_INT3; PC_nHSE_Sel <= 1'b1; Inhibit_Context_Switch <= 1'b0; end end else begin PC_nHSE_Sel <= 1'b0; if((Reg_Write_nHSE_WB==1)&(WB_OpCode==Op_Type_CP2)&(WB_Rs==Rs_Type_CTC2)&((WB_Immediate == 16'h0001)&((Write_Data_WB&32'h00000080)== 32'h00000000))) begin grInt_select_sCPU[sCPU3_ID] <= 8'hFF; grEv_select_sCPU[sCPU3_ID] <= 3'b111; end end end end //for end // mutex else if(((crTRi[sCPU3_ID] & Mask1_bit5)&&(crEVi[sCPU3_ID] & Mask1_bit5))&& (~((crEPRi3[20:18]