Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 19 06:56 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 2962496
minstret = 713757
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n2n512n2n4n2n160n2n1n1n2/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           6506715500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 6506715500 ps
CPU Time:   1185.340 seconds;       Data structure size:   2.6Mb
Sun Nov 19 07:16:37 2023
