Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Oct 13 09:12 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 201514
minstret = 191795
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n8n128n16n8n4n96n2n2n1n8/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           5739365500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5739365500 ps
CPU Time:   1843.850 seconds;       Data structure size:   4.2Mb
Fri Oct 13 09:43:29 2023
