Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 19 05:55 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 2626360
minstret = 714309
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n2n256n16n4n4n96n1n1n1n24/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           5833135500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5833135500 ps
CPU Time:   1112.200 seconds;       Data structure size:   3.9Mb
Sun Nov 19 06:14:12 2023
