Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 18 13:30 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1920965
minstret = 714275
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n4n2048n2n2n3n32n1n3n1n4/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           4425385500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 4425385500 ps
CPU Time:    840.360 seconds;       Data structure size:   2.9Mb
Sat Nov 18 13:44:59 2023
