Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 17 20:46 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 3372264
minstret = 713717
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n2n256n2n2n2n32n1n2n1n2/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           7325975500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 7325975500 ps
CPU Time:   1106.640 seconds;       Data structure size:   2.2Mb
Fri Nov 17 21:05:19 2023
