Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 17 05:18 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 2788311
minstret = 714325
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n2n512n2n8n3n160n1n3n1n4/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           6156995500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 6156995500 ps
CPU Time:   1126.320 seconds;       Data structure size:   3.6Mb
Fri Nov 17 05:37:17 2023
