Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 20 02:37 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1666413
minstret = 714353
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom32n2n256n8n8n2n96n1n2n1n16/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           3913335500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 3913335500 ps
CPU Time:    765.260 seconds;       Data structure size:   3.8Mb
Mon Nov 20 02:49:50 2023
