Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 16 18:26 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1837810
minstret = 714279
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom32n2n128n2n10n4n96n1n4n1n16/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           4255195500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 4255195500 ps
CPU Time:    989.380 seconds;       Data structure size:   4.0Mb
Thu Nov 16 18:42:47 2023
