Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 17 13:41 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 3023618
minstret = 714359
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n2n128n16n2n3n128n1n1n2n8/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           6627705500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 6627705500 ps
CPU Time:   1202.060 seconds;       Data structure size:   3.0Mb
Fri Nov 17 14:01:25 2023
