Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 16 23:41 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 2223231
minstret = 714243
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom32n2n128n2n2n1n32n1n1n1n4/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           5027685500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5027685500 ps
CPU Time:    749.150 seconds;       Data structure size:   2.2Mb
Thu Nov 16 23:54:13 2023
