Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 13 15:57 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1151192
minstret = 714275
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n8n2048n2n2n4n128n2n2n1n16/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           2885685500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2885685500 ps
CPU Time:    723.780 seconds;       Data structure size:   3.9Mb
Mon Nov 13 16:09:27 2023
