Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Oct 19 22:04 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 2591919
minstret = 2058917
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n4n256n4n2n3n64n2n1n2n8/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           5765295500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5765295500 ps
CPU Time:   1599.650 seconds;       Data structure size:   2.9Mb
Thu Oct 19 22:30:45 2023