Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 14 02:55 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 2623507
minstret = 714347
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n2n2048n8n10n5n64n1n5n2n16/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           5830205500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5830205500 ps
CPU Time:   1216.610 seconds;       Data structure size:   6.2Mb
Tue Nov 14 03:15:38 2023
