Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 10 02:30 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1101686
minstret = 714265
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n8n2048n2n2n4n160n2n1n2n24/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           2787285500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2787285500 ps
CPU Time:    706.080 seconds;       Data structure size:   4.2Mb
Fri Nov 10 02:42:41 2023
