Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Oct 21 16:21 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1162449
minstret = 714297
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n8n1024n2n4n3n160n1n1n1n8/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           2906885500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2906885500 ps
CPU Time:    624.350 seconds;       Data structure size:   3.2Mb
Sat Oct 21 16:32:20 2023
