Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 15 22:36 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 2823508
minstret = 714195
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n2n128n8n4n1n96n1n1n1n2/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           6227935500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 6227935500 ps
CPU Time:    930.270 seconds;       Data structure size:   2.4Mb
Wed Nov 15 22:51:55 2023
