Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Oct 24 00:22 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1164933
minstret = 714277
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n8n512n4n2n3n160n2n1n1n8/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           2910515500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2910515500 ps
CPU Time:    655.260 seconds;       Data structure size:   3.3Mb
Tue Oct 24 00:33:51 2023
