Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 17 18:12 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 2637967
minstret = 714329
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n2n1024n2n10n4n128n1n4n1n16/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           5857085500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5857085500 ps
CPU Time:   1189.170 seconds;       Data structure size:   4.3Mb
Fri Nov 17 18:32:39 2023
