Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 16 02:37 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 3550890
minstret = 713781
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n2n128n2n2n2n32n1n2n1n2/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           7682955500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 7682955500 ps
CPU Time:   1140.380 seconds;       Data structure size:   2.2Mb
Thu Nov 16 02:56:10 2023
