Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 18 02:36 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 2696232
minstret = 714359
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n2n2048n2n10n5n160n1n5n1n8/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           5975785500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5975785500 ps
CPU Time:   1312.270 seconds;       Data structure size:   4.4Mb
Sat Nov 18 02:58:05 2023
