Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 19 23:23 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1316467
minstret = 714323
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n8n128n8n8n3n128n1n3n1n8/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           3212315500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 3212315500 ps
CPU Time:    700.920 seconds;       Data structure size:   3.7Mb
Sun Nov 19 23:35:18 2023
