Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 15 01:07 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1311369
minstret = 714337
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom16n8n256n4n2n4n32n1n4n1n24/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           3202385500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 3202385500 ps
CPU Time:    711.400 seconds;       Data structure size:   3.4Mb
Wed Nov 15 01:19:17 2023
