Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 19 19:24 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1092356
minstret = 714347
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom32n16n1024n8n10n4n96n2n4n2n24/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           2765455500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2765455500 ps
CPU Time:    736.010 seconds;       Data structure size:   5.8Mb
Sun Nov 19 19:36:30 2023
