Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 17 12:34 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1647417
minstret = 714265
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom32n2n2048n4n8n3n128n1n2n1n24/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           3878125500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 3878125500 ps
CPU Time:    859.520 seconds;       Data structure size:   5.1Mb
Fri Nov 17 12:48:50 2023
