Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 17 11:01 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1661282
minstret = 714255
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom32n2n256n4n6n2n160n2n1n2n8/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           3903275500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 3903275500 ps
CPU Time:    744.160 seconds;       Data structure size:   3.0Mb
Fri Nov 17 11:13:31 2023
