Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 15 16:47 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1333772
minstret = 714221
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom32n4n256n4n4n2n64n2n2n2n4/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           3248205500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 3248205500 ps
CPU Time:    615.860 seconds;       Data structure size:   2.7Mb
Wed Nov 15 16:57:17 2023
