Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 19 11:39 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1273494
minstret = 714291
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom32n4n256n8n10n4n32n2n4n1n24/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           3126535500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 3126535500 ps
CPU Time:    845.630 seconds;       Data structure size:   4.6Mb
Sun Nov 19 11:53:42 2023
