Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 17 17:46 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1377924
minstret = 714281
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n2n256n8n2n4n128n2n4n1n8/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           3335465500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 3335465500 ps
CPU Time:    720.020 seconds;       Data structure size:   3.1Mb
Fri Nov 17 17:58:54 2023
