Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Nov 19 02:47 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1364280
minstret = 714303
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n2n512n2n4n2n32n1n2n1n8/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           3309555500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 3309555500 ps
CPU Time:    580.510 seconds;       Data structure size:   2.6Mb
Sun Nov 19 02:56:42 2023
