Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Oct 22 04:42 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1170751
minstret = 714303
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n8n128n16n2n2n160n2n2n1n16/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           2921815500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2921815500 ps
CPU Time:    593.470 seconds;       Data structure size:   3.4Mb
Sun Oct 22 04:52:23 2023
