Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Oct 21 22:28 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1182116
minstret = 714255
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n8n256n8n4n2n128n2n1n1n4/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           2944895500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2944895500 ps
CPU Time:    557.490 seconds;       Data structure size:   3.0Mb
Sat Oct 21 22:37:48 2023
