Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version R-2020.12-1_Full64; Runtime version R-2020.12-1_Full64;  Oct 20 01:01 2023
[UART] UART0 is here (stdin/stdout).
C0: reg block 4x5x6, cache block 40x50x60
mcycle = 1147979
minstret = 714357
$finish called from file "/proj/users/hanwei.fan/dataset/generated-src/chipyard.harness.TestHarness.Boom64n8n512n4n8n5n160n2n2n1n24/gen-collateral/TestDriver.v", line 158.
$finish at simulation time           2876025500
           V C S   S i m u l a t i o n   R e p o r t 
Time: 2876025500 ps
CPU Time:    822.210 seconds;       Data structure size:   4.9Mb
Fri Oct 20 01:14:46 2023
